Contact Plating:
FPGA SRAM:
Height Seated (Max):
JESD-609 Code:
Minimum Operating Temperature:
Moisture Sensitivity Level (MSL):
Number of CLBs:
Number of Equivalent Gates:
Number of Gates:
Number of I/Os:
Number of Logic Elements/Cells:
Number of Pins:
Number of Terminals:
Number of Terminations:
Operating Supply Voltage:
Package:
Part Status:
Pbfree Code:
Peak Reflow Temperature (Cel):
Product Status:
Propagation Delay:
Qualification Status:
Reach Compliance Code:
Speed Grade:
Supplier Package:
Supply Voltage:
Temperature Grade:
Terminal Position:
Time@Peak Reflow Temperature-Max (s):
Voltage - Supply:
FPGA Registers:
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