SPC8548PXAUJB

SPC8548PXAUJB Description

A high-level description of the features of the gadget is given in this section. The main functional components of the gadget are depicted in the accompanying figure. Although the MPC8548E is the focus of this article, the majority of the information also applies to the MPC8547E, MPC8545E, and MPC8543E family members. Specific variations, such as pinout variations and CPU frequency ranges, are noted as such. Consult the MPC8548E PowerQUICC III Integrated Host Processor Reference Manual for specific PVR and SVR numbers.

SPC8548PXAUJB Features

• Programmable timing supporting DDR and DDR2 SDRAM

• 64-bit data interface

• Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

• DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports

• Full ECC support

• Page mode support

• Contiguous or discontiguous memory mapping

• Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions

• Sleep mode support for self-refresh SDRAM

• On-die termination support when using DDR2

• Supports auto-refreshing

SPC8548PXAUJB Applications

• Power Management

• Consumer Electronics

• Portable Devices

• Industrial